Circuits in SSI -- I

You really ought to do this lab in teams of two or three if you wish.

Getting ready

We're learning. After the mess with downloading diglog input files with netscape, we've decided to put all input files used by this lab into a single ZIP file. We're also going to package diglog and espresso into one ZIP. Go ahead and download and unZIP both of these into

The problem

This time, you'll "build" a four-input circuit which can be used with a seven-segment display to show for the digits 0 to 9, a blank, and the letters 'unca' in lower case. Let the digits 0 to 9 be binary 0000 to 1001, let the blank be 1011, and let the letters of unca be 1100 to 1111. Binary 1010 will be a don't care. We'll call this the UNCA 7-segment decoder.

 _         _    _         _    _    _    _    _                    _    _    _ 
| |    |   _|   _|  |_|  |_   |_     |  |_|  |_|   ???       | |  | |  |     _|
|_|    |  |_    _|    |   _|  |_|    |  |_|   _|   ???       |_|  | |  |_   |_|

You should already have a diglog circuit specification for the entire circuit, which you downloaded above and stored in files lab6main.lgf (3796 bytes) and lab6unca.lgf (9287 bytes). Start up diglog and load lab6main.lgf. Nothing seems to be happening. However, notice the words "PAGE 1 OF 1" in the upper-right hand corner of the screen. Now type the digit 2. This will take you in a new empty page. Now load lab6unca.lgf. This circuit is actually a solution to the whole problem. Type 1 to return to the main circuit. It should now be running.

The circuit on page 2 is a module for the circuit on page 1. Effectively the instance gate at the bottom of page 1 is replaced with a copy of the circuit on page 2. You can consider the instance gate at the bottom of page 1 is similar to a C++ procedure call with its actual parameters, while the instance gate at the top f page 2 is similar to a C++ procedure header with its formal parameters. By the way, note that the circuit on page 2 doesn't really "run". That's because it may be used several times by circuits on other pages.

Task one

First, write up the espresso input for the entire UNCA 7-segment program and run in in diglog. By the way, the first ten of the sixteen rows of the espresso input were "published" in Lab 5. Your output should look like the following:

.i 4
.o 7
.p 12
001- 0001001
01-0 0010001
1--0 0001100
0-11 1110000
-00- 0110000
1101 1110110
-110 1001110
100- 1001011
0101 1011011
--00 0110010
1111 1111101
-0-0 1101100

Now you are to choose either one or two segments to implement on your own, except that you can't choose the bottom left segment, e, alone. It is just too easy. Go ahead and create espresso input for your chosen segment(s) and run espresso on your file. Show the corresponding output to the instructor.

What to do next

Let's suppose we were allowed to chose the forbidden segment e. First of all, we'd generate the appropriate espresso input. That's easy. We'll just go back to the file created for task one and remove all but the fifth output column. We then run espresso and are rewarded with the following output.

.i 4
.o 1
.p 3
-0-0 1
11-- 1
--10 1

We then go back into the "main" circuit and replace the empty middle with a combinational circuit with three two-input NAND gate and one three-input NAND gate implementation that implements the e segment. We also then connect the output of this new circuit to an array of LED's and compare it with the original.
Segment E

Task two

In your groups, choose one or two segments to implement. Modify the espresso input file, run espresso, and use diglog to implement the circuit with NAND gates and inverters just like you did in Homework 5. Show your work to the lab instructor.

Task three

Now suppose you needed to implement this circuit with 7400 SSI chips. These chips are packaged as follows:

6 inverters
4 2-input NAND gates
3 3-input NAND gates
2 4-input NAND gates
1 8-input NAND gate

Go back to your diglog solution and for each gate add a label that specifies how that gate will be implemented. For example, beside a 4-input NAND gate you might enter "One half 7420." Remember that in some instrance it might be reasonable to "upgrade" a NAND gate to reduce the number of packages required by your design.
Segment E for 7400

Use diglog's label command to add the names of all your team members to the circuit and save the circuit. FTP it to your UNCA CSCI workstation account and save it in your directory csci/255 under the name home6.lgf. Be sure to use binary mode when you transfer the file.

Task Four

Obtain from your lab instructor an ASCII chart of common 7400 chip packages. (Incidently, this information is available from the Chip Directory.) Use this form to create a schematic of an SSI implement of your circuit assigning the inputs and outputs of the NAND gates and inverters of your diglog circuit to the inputs and outputs of the 7400 chips you would use in an SSI implementation. Show the schematic to your lab instructor.

By the way, here's a schematic for segment e.

      B1--------->>1 -|1A   Vcc|- 14
          Vcc---->>2 -|1B    4A|- 13<--------B3
      B1'<<--------3 -|1/Y   4B|- 12<----Vcc   
      B1'-------->>4 -|2A   4/Y|- 11------->>B3'
      B3'-------->>5 -|2B    3A|- 10<--------B0
      (B1'B3')'<<--6 -|2/Y   3B|-  9<--------B1
                   7 -|gnd  3/Y|-  8-->>(B0 B1)'
      B2--------->>1 -|1A   Vcc|- 14 
      B3'-------->>2 -|1B    1C|- 13<----Vcc    
      (B1'B3')--->>3 -|2A    1Y|- 12->>(B2 B3')'
      (B0 B1)'--->>4 -|2B    3C|- 11 
      (B2 B3')'-->>5 -|2C    3B|- 10 
      output----->>6 -|2Y    3A|-  9 
                   7 -|gnd   3Y|-  8 

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