//	Dean Brock -- April, 1997
//
// This is a Example 2 of a combintorial circuit
//

// This time the circuit is specified as a gate-level model
// in which wires are used to connect gates.

// Note the natural relationship with the diglog specification.
module comboCircuit(Z, jA, kA, jB, kB, X, Y, A, B) ;

output Z, jA, kA, jB, kB ;
input  X, Y, A, B ;
wire notX, notY , notA, notB;
wire P1, P2, P3, P4, P5 ;

  not  g01(notA, A) ;
  not  g02(notB, B) ;
  not  g03(notX, X) ;
  not  g04(notY, Y) ;
  nand g05(P1, X, Y, A, B) ;
  nand g06(P2, X, notY) ;
  nand g07(P3, notX, Y, notA, B) ;
  nand g08(P4, notX, Y) ;
  nand g09(P5, X, notY, A) ;
  not  g10(Z, P1) ;
  nand g11(jA, P2, P3) ;
  not  g12(kA, P1) ;
  nand g13(jB, P4, P5) ;

  nand g14(kB, P1, P3) ;

endmodule

module simulate ;

reg inX, inY, inA, inB ;
wire outZ, outJA, outKA, outJB, outKB ;

  comboCircuit C(outZ, outJA, outKA, outJB, outKB, inX, inY, inA, inB) ;

initial
begin
  #3 ;
  {inX, inY, inA, inB } = 4'b0000 ;
  #5 ;
  {inX, inY, inA, inB } = 4'b0001;
  #5 ;
  {inX, inY, inA, inB } = 4'b0010;
  #5 ;
  {inX, inY, inA, inB } = 4'b0011;
  #5 ;
  {inX, inY, inA, inB } = 4'b0100;
  #5 ;
  {inX, inY, inA, inB } = 4'b0101;
  #5 ;
  {inX, inY, inA, inB } = 4'b0110;
  #5 ;
  {inX, inY, inA, inB } = 4'b0111;
  #5 ;
  {inX, inY, inA, inB } = 4'b1000;
  #5 ;
  {inX, inY, inA, inB } = 4'b1001;
  #5 ;
  {inX, inY, inA, inB } = 4'b1010;
  #5 ;
  {inX, inY, inA, inB } = 4'b1011;
  #5 ;
  {inX, inY, inA, inB } = 4'b1100;
  #5 ;
  {inX, inY, inA, inB } = 4'b1101;
  #5 ;
  {inX, inY, inA, inB } = 4'b1110;
  #5 ;
  {inX, inY, inA, inB } = 4'b1111;
  #5 ;
  $finish ;
end

initial
begin
  $display("") ;
  $display("Example 01") ;
  $display("") ;
  forever
  begin
    #5 ;
    $display("(%b,%b,%b,%b) -> %b,%b,%b,%b,%b",
	     inX, inY, inA, inB, outZ, outJA, outKA, outJB, outKB) ;

  end
end


endmodule