17 April, 1996
Why is good branch prediction important in a modem microprocessor?
The SPARC processor has pages of 8192 bytes and virtual addresses of 32 bits. How are the virtual addresses divided into virtual page numbers and page offsets?
Suppose a computer has a physical memory (RAM) of 16M 24 bits and a four-way set associative cache of 512k words organized into blocks of eight words. How are the physical addresses of the computer broken into tag, index, and word offset bits? Draw a diagram showing the physical organization of the cache.
D = A * A + 4 * B X = B * X Y = A + X Describe how to efficiently execute this code on a computer with RISC-like instruction set with load delay slots of size two? (Note: This means you need two instructions between storing and fetching register!)
Consider the following loop for storing the ten thousand squares of the integers from 1 to 10,000 into an array SQ.
DO 100 N =1, 10000 100 SQ(N) = N*N
What sort of techniques would a compiler use to generate efficient code for this loop on a superpipelined computer like the Pentium Pro or Alpha AXP?
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