# Final exam -- Open book section

9 May, 1995

The entire exam is to be turned in at 7:00 PM. Work the closed book section first and turn it in before you consult your books and notes to work on the open book section.

## Problem 1. (4 points)

Translate the following expression into Reverse Polish Notation:

• (A + B * C) * (X + Y)

## Problem 2. (4 points)

If a two-dimensional array A of integers is of size 1000 by 1000, which of the following nested loops is likely to executed faster when run on most of today's microprocessors:

```     for (i=0; i<1000; ++i)
for (j=0; j<1000; ++j)
A[i][j] = 5 ;

for (j=0; j<1000; ++j)
for (i=0; i<1000; ++i)
A[i][j] = 6;
```

## Problem 3 (4 points)

Almost all modern microprocessors have two L1 caches, one for data and another for instructions. Why is the L1 cache divided into two parts?

## Problem 4 (4 points)

Almost all modern microprocessors have a single L2 cache that holds both data and instructions. Why?

## Problem 5 (6 points)

The 486 has a cache invalidation instruction to invalidate the contents of the cache. This instruction is restricted to supervisor mode.

Why is this instruction needed?

Why is this instruction restricted to supervisor mode?

Unfortunately, there is a bug in the implementation of many 486 chips that allow the cache invalidation instruction to be executed outside of supervisor mode. Why is this bug not considered a problem? (In fact, the bug went unnoticed for several years.)

## Problem 6 (4 points)

In almost all computers, integers are stored in twos-complement notation, rather than signed magnitude, to increase performance. Why is twos-complement representation considered more efficient?

## Problem 7 (4 points)

In almost all computers, floating point numbers are stored in signed magnitude notation, rather than twos-complement, to increase performance. Why is signed magnitude representation considered more efficient?

## Problem 8 (4 points)

A machine supporting 32-bit virtual addresses has a four-way associative cache with 4096 entries. Describe the structure of the cache and the process of looking up addresses in the cache.

## Problem 9 (4 points)

The PowerPC chip has an EIEIO instruction (seriously, it does). This instruction is a "memory barrier" instruction. The EIEIO makes sure that all write-throughs resulting from previous instructions are completed before any write-throughs resulting from future instructions complete. Where do you expect the EIEIO to be used in PowerPC programs?

## Problem 10 (4 points)

Name four features of modern microprocessors that have made life more difficult for compiler writers.

## Problem 11 (4 points)

Consider the hardware setup shown in Figure 10-5 (p. 341) to multiply two integers. If this setup is used to multiply the sixteen-bit multiplicand 0110110010010010 by the sixteen-bit multiplier 0011111000000001, what is stored in the Q register at the end of the fifth step of the iteration of the algorithm shown in Figure 10-6 (p. 342)?

## Problem 12 (4 points)

Conditional codes, sometimes called status bits or flags, are very popular in older computer architectures, but generally are not used in more recent processors. Why do you think this is so?

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