# Final exam -- Open book section

10 May, 1994

The entire exam is to be turned in at 4:10 PM. Work the closed book section first and turn it in before you consult your books and notes to work on the open book section.

## Problem 1. (4 points)

Translate the following expression into reverse Polish notation (RPN):

• A + E * (F + G) + B

## Problem 2. (9 points)

Show how to compute the following C statements

```     x := u + v + w ;
y := a * x ;
```

in the machine language of a generic RISC processor (pp. 259-260) with LOAD and STORE instructions that use one memory and one register address and with arithmetic operations that use three register addresses. Your code should vaquely resemble assembler code for the MIPS and Alpha AXP processors.

## Problem 3. (6 points)

The Alpha AXP processor has an instruction S8ADDQ such that

sets register Rc to 8*Ra+Rb. This is a rather specialized instruction for a RISC processor. Why did the designers of the Alpha AXP include it? Where will it be used?

## Problem 4. (6 points)

Consider the following loop which the copies the second row of an array A into the first row:

```     for (i=0; i<1024; ++i)
A[1][i] = A[2][i] ;
```

Oddly enough, on many modern microprocessors, this loop will run significantly faster if A is declared to be of dimension 1037×1037, that is,

```     int A[1037][1037] ;
```

rather than the more natural 1024×1024. Explain why this happens?

## Problem 5. (6 points)

Suppose a CSCI 320 student made the following observation:

"DMA is an outdated notion that should be abandoned in this error of RISC processors. The DMA interface just steals cycles from the CPU. If the cycles are going to be lost anyway, you might as well have the CPU transfer the data rather than introducing these cumbersome DMA transfer methods."

Comment on the validity of this observation.

## Problem 6. (4 points)

Why is the CPU bus on the PowerMac twice the width of the registers of the PowerPC?

## Problem 7. (4 points)

How does a processor like the IBM PC, that supports isolated I/O, use the same bus for both I/O and memory accesses?

## Problem 8. (4 points)

The recently introduced Motorola 68060 has pages of 4096 bytes and virtual addresses of 32 bits. How are the virtual addresses divided into virtual page numbers and page offsets?

## Problem 9. (4 points)

Suppose a token ring interface that makes DMA transfers using cycle stealing is attached to a a bus that is 32 bits wide and has a cycle time of 100 nsec. The token ring interface can send and receive data at the rate of 16,000,000 bits per second. If the token ring is transfering data to memory at its full rate, how often must it steal a cycle?

## Problem 10. (4 points)

The decimal number 777,777,777 is the binary number 101110010110111111001001110001. How is 777,777,777 stored in a 32-bit floating point number with a one bit sign field, an eight bit exponent field stored with a bias of 127, and a 23 bit mantissa field?

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