This assignment is due in-class by 28 November or may be submitted to Homework Cache on moodle by 6:55 PM on 26 November.
You should read sections 6.4.1 to 6.4.3 of the textbook before doing this assignment.
This exact same problem was done in the Spring 2017 CSCI 255 and the Fall 2016 CSCI 255. You may pester students from those semesters for help!
A real-life problem
The Intel 486DX was a 32-bit computer introduced in 1989. The 486DX had a 4-way set associative 8k (8192) byte cache and each block (line, in Intel parlance) of the cache was 16 bytes. If you prefer the textbook’s variables: m is 32, C is 8k, B is 16, and E is 4.
Now answer some subquestions
How many blocks (or lines) did the 486DX cache have?
How many sets (or rows) did the 486DX cache have? (It is a tad confusing that rows and lines have different meanings.)
The 32-bit address is divided into three fields: tag, index, and offset. How many bits are each allocated in each of these fields?
What are the tag, index, and offset fields of the address 0x2017DEED?
Illustrate the entire cache structure with a drawing.