FSM implemented in SystemVerilog
module labfsm
(input logic clk,
input logic reset,
input logic x,
output logic q) ;
typedef enum logic [2:0] {A, B, C, D, E} statetype ;
statetype pres_state, next_state ;
always_ff@(posedge clk, posedge reset)
if (reset)
pres_state <= A ;
else
pres_state <= next_state ;
always_comb
case (pres_state)
A:
if (x) next_state = B ;
else next_state = A ;
B:
if (x) next_state = B ;
else next_state = C ;
C:
if (x) next_state = D ;
else next_state = A ;
D:
if (x) next_state = E ;
else next_state = C ;
E:
if (x) next_state = B ;
else next_state = C ;
default:
next_state = A ;
endcase
assign q = (pres_state == E) ;
endmodule