# Fall 2016 CSCI 255 Homework 10

This assignment is due in-class or may be submitted to Homework 10 on moodle by 5:10 PM on 1 December.

You should read sections 8.3 and 8.4 of the textbook before doing this assignment.

## Problem 1

The Intel 486DX was a 32-bit computer introduced in 1989. The 486DX had a 4-way set associative 8k (8192) byte cache and each block (line, in Intel parlance) of the cache was 16 bytes. If you prefer the textbookâ€™s word oriented terminology: The 486DX had a 2k word cache with blocks of 4 words where each word is 4 bytes.

### Subproblem 1A

How many blocks (or lines) did the 486DX cache have?

### Subproblem 1B

How many sets (or rows) did the 486DX cache have? (It is a tad confusing that rows and lines have different meanings.)

### Subproblem 1C

The 32-bit address is divided into three fields: tag, index, and offset. How many bits are each allocated in each of these fields?

### Subproblem 1D

What are the tag, index, and offset fields of the address 0xE1E1E1E0?

### Subproblem 1E

Illustrate the entire cache structure with a drawing.

## Problem 2

Do Exercise 8.20 of the textbook.