This assignment *must* be turned in class
on *Friday* 18 September.

## The problem

It is claimed that a “popular interview” question for Computer Engineers is to design a Moore finite state machine that outputs a 1 if and only if its input bitstring encodes a number evenly divisable by 5. For example, after the input sequence 1000001101 (525 in decimal) is received, the output should be 1.

To make the task a bit easier (and more mathematical),
the *empty* input string is defined as divisible by five.

Note that the FSM really doesn’t *know* the last bit of
the input, so it must produce its output incrementally as shown in
the table below:

input | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|

output | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 |

The 1’s are output after receiving the empty bit string, 1000001 (65), 1000001101 (525), 10000011010 (1050), and 100000110100 (2100).

### Not the problem

This is *not* the *divide by n* where
an FSM outputs 1 every five clock cycles.
That would be a

*frequency divider*.

### Also not the problem

The number is being received MSB (most significant bit) first, not LSB (least significant bit) first.

### Also not the problem

The FSM is *not* counting if number of 1’s in
the input stream is divisible by 5.

### Most certainly not the problem

The inputs to FSM are *not* decimal digits.
That’s a problem to torment students in a formal language course.

## What to turn in

I know that you can find many solutions to this problem using
a search engine called Google.
That’s OK; but you must cite your sources and you
*must* turn in a beautifully hand-drawn FSM state diagram
and a FSM state and output table.

You will not get a 10 unless the diagram has artistic merit.