Fall 2014 CSCI 255 Homework 4

This assignment is due in class on 15 September or may be uploaded to Homework 4 on moodle by 2:00 PM on 14 September.

Problem 1

Below are three addition problems. Convert the numbers in these problems into 8-bit twos-complement and then add as 8-bit twos-complement. Some of these additions will result in overflow.

Indicate the result of each addition and note if the addition results in overflow.

Problem 2

Perform the following operations and express the result as it should be for CSCI 255.

Problem 3

Problem 4

The final problem is preparation for the next homework.

Below are a couple of methods from a Java program that implements the actions of a finite state machine. Either draw a diagram or create a table to represent this finite state machine.

    enum State { S0, S1, S2 } ;
    
    private static char output(State presState) {
        return presState == State.S0 ? '1' : '0' ;
    }

    private static State nextState(State presState, char inChar) {
        State nxtState ; 
        if (inChar == '0') {
            if (presState == State.S0) {
                nxtState = State.S0 ;
            } else if (presState == State.S1) {
                nxtState = State.S2 ;
            } else /* presState == State.S2*/ {
                nxtState = State.S1 ;
            }
        } else /* inChar == '1' */ {
            if (presState == State.S0) {
                nxtState = State.S1 ;
            } else if (presState == State.S1) {
                nxtState = State.S0 ;
            } else /* presState == State.S2*/ {
                nxtState = State.S2 ;
            }
        }
        return nxtState ;
    }

If you wish to run this program, you can download a ZIPped NetBeans project file to try it out.

You can also get a headstart on CSCI 320 and try out a SystemVerilog implementation of the finite state machine.

module MysteryFSM(input  logic clk, 
                  input  logic reset, 
                  input  logic d,
                  output logic q);

  typedef enum logic [1:0] {S0, S1, S2} statetype;
  statetype state, nextState;

  // state register
  always_ff @(posedge clk, posedge reset)
    if (reset) state <= S0;
    else       state <= nextState;

  // next state logic
  always_comb
    case (state)
      S0: 
        case (d)
          0:  nextState <= S0 ;
          1:  nextState <= S1 ;
        endcase
      S1:
        case (d)
          0:  nextState <= S2 ;
          1:  nextState <= S0 ;
        endcase
      S2:
        case (d)
          0:  nextState <= S1 ;
          1:  nextState <= S2;
        endcase
      default:
        nextState <= S0;
    endcase


  // output logic
  assign q = (state == S0);
endmodule