• Homework 1
• three new gates
  • NAND
  • NOR
  • XOR
• De Morgan’s Laws
  • (P Q)' ≡ P' + Q'
  • (P + Q)' ≡ P' Q'
• Implementing gates with MOSFET
  • Invertor (NOT)
  • NAND
  • NOR
  • AND as NOT-NAND
  • OR as NOT-NOR
• transistor counts
  • n input NAND or NOR: 2 n
  • NOT: 2
  • n input AND or OR: 2 n + 2
• implementing canonical sum-of-products (AND-OR) with NAND’s (NAND-NAND)