CSCI 255 Lab 4 -- Building Logic Gates from Transistors

Background material for this lab was taken from a laboratory exercise developed by W. J. Dally for “CS 99S: The Coming Revolution in Computer Architecture: What To Do With One Billion Transistors,” a course offered at Stanford University in 2001.


You will need the following equipment and components to create the circuits in today's lab:


We can perform many control functions by connecting two switches, or two transistors, in series or parallel. In the examples below, we are using two NPN transistors to connect the output to ground, or pass 0. In the circuit on the left, the terminal c will be connected to 0 if inputs a and b are both 1. Similarly, on the right, the terminal f will be connected to 0 if either d or e is 1.
serial & parallel
The NPN networks above can not pass 1. Either they pass 0, or they are effectively disconnected from their output terminal.

We can build similar series and parallel circuits out of PNP transistors. These circuits can be used to pass 1 to a terminal when appropriate inputs are applied to the base connections of the PNP transistors.

While the above examples were two-input series and parallel networks, we can extend these circuits to handle an arbitrary number of inputs. When compatible NPN and PNP transistor networks are connected as illustrated below, complex boolean functions can be implemented.

The NPN and PNP networks must be designed so that there is no input combination in which both networks pass a value at the same time. If one network were passing 1 and the other were passing 0, we would have a short-circuit.

There are additional and more esoteric properties of transistors that restrict how they can pass values. This approach to implementing logic functions with transistors only works for inverting logic functions. In an inverting logic function, changing any input line from 0 to 1 will never change the output line from 0 to 1. This means that a non-inverting logic gate, such as the AND, must be built with two inverting logic gates, such as NAND followed by NOT.

Part 1: Making an Inverter

The simplest circuit built with PNP and NPN networks is the inverter. Here is how NOT can be implemented with CMOS.
CMOS inverter

The PNP network is a single pMOS transistor and the NPN network is a single nMOS transistor. When the input is a 1, the NPN network passes 0 and the PNP network is disconnected. Consequently, the output is 0. Similarly, when the input is 0, the output is connected to 1 via the PNP network.

When inverters are built with different logic families, they have radically different implementations. For example, here is one way to realize an inverter in the TTL (transistor-transistor logic) family.
TTL inverter

Today, integrated circuits are implemented in some form of CMOS. A few decades before that, TTL was common. In this lab we are going to go back about fifty years to RTL (resistor-transistor logic), because it's not hard to make RTL circuits on a breadboard.

An RTL inverter can be implemented with a couple of resistors and a single transistor as shown below. The input to the invertor is connected to the transistor though a base resister, Rbas. There is a collector resistor, Rcol, that connects the high voltage to the collector of the transister. We will use a 1K Ω registor for Rcol and a 10K Ω register for Rbas. There's nothing magic about these choices. We just happen to have a lot of them. The emitter of the transistor is directly connected to ground.
RTL inverter
In the drawing above the triangle at the top is a connection to VDD and the triangle at the bottom is a connection to ground.

You should be wondering what happened to the PNP network. Well, it's just not there. There is a one-transistor NPN network that can pass 0 to the output. If it doesn't, then a single pull-up resistor (Rcol) will provide 1 as the “default” output. When the NPN circuit is passing 0, the transistor is active and connects the output to ground.

So why would anyone use two-transistor CMOS rather than one-transister RTL? There are several reasons. First, today's computers are implemented with integrated circuits. The area required for a resistor on a chip is much larger than that required for a transistor. Second, because the 1 must be “pulled” through a resistor, it requires some time to charge up the output line when the output changes from 0 to 1. (Think of filling a swimming pool with a garden hose.) In CMOS, this is almost instantaneous. Third, when the 1 is being generated by the pullup, it requires constant power and, consequently, produces heat. (Think of leaving the water running all the time.) In CMOS, power is not used when the circuit is in a stable state. The CMOS FET (field-effect transistor) is very similar to a switch. It is either off or on. The BJT (bipolar junction transistor) used in RTL is a bit more like an amplifier. It is happier in the analog world.

In the first part of the lab we are going to ask you to build four NOT gates and two LED switches. You need the switches because it would be very tedious to test your circuit with a multimeter.

We suggest that on one end of your breadboard, you create the two LED switches. Each is a single-input circuit that lights up an LED when the circuit's input is 1.
LED schematic   LED on breadboard

Because the NOT and the LED switch circuits are very similar, you should build and test the LED switchs first.

Place the four NOT's in the middle of the breadboard. We recommend that you put the NPN transistor and the collector resistor on the bottom half of your breadboard and use the base resistor to bridge between the top and bottom halves of the baseboard.


Be sure to test your inverters and LED switches before showing them to your instructor.

Show your LED switches and NOT circuits to your instructor.  

Part 2: A NOR Gate

In CMOS Boolean functions are generally implemented with NAND gates. Unfortunately, it is difficult to build a reliable NAND gate having more than two inputs with RTL. So, we are going to build a NOR. This is not a significant problem when building larger circuits. Any Boolean function can be implemented with two levels of NOR gates use a product of sums, similar to how a sum of products can be used in a two-level NAND implementation.

Here's an RTL circuit for a two-input NOR.

Now if you are thinking that an NOR looks like two NOT's sharing a single pull-up transistor Rcol, you are on the right track.
RTL inverter + RTL inverter ~= NOR in RTL
But it's even better than that because two 1K Ω resistors in parallel make a 500 Ω resistor and a 500 Ω resistor is good enough for our NOR. (This means you don't even have to remove the extra 1K Ω resistor to build your NOR.)

By the way, the Apollo Guidance Computer used about 2,800 RTL chips, each containg two three-input NOR gates, for all the manned flights to the moon. If you click the image below, you will see that our NOR differs little from NASA's.
AGC 3-input NOR

Now create your own version of this 1965 classic with a single NOR from two NOT's by adding one wire!


Demonstrate the functionality of your NOR gate for your instructor.  

Part 3: An OR Gate

So, now you have one NOR and two NOT's. Take advantage of the following Boolean identity to build an OR gate.


Demonstrate the functionality of your OR gate for your instructor.  

Part 4: An AND Gate

Next use De Morgan's law to build an AND gate.


Demonstrate the functionality of your AND gate for your instructor.  

Preview of coming events: The SR flip-flop

Don't tear up your breadboard. Next week, you'll build a SR flip-flop from two NOR gates.
SR from NOR