library IEEE;
use IEEE.std_logic_1164.all;

entity Lab6 is
    port (
        RST: in STD_LOGIC;
        MyIn: in STD_LOGIC;
        CLK: in STD_LOGIC;
        MyOut: out STD_LOGIC
    );
end Lab6;

architecture Lab6_arch of Lab6 is
  type count_int is range 0 to 3 ;

begin
  process(CLK)
  variable trans_count: count_int ;
  begin
    if CLK'event and CLK = '1' then
      if RST='1' then
        trans_count := 0 ;
        MyOut <= '0' ;
      elsif (trans_count mod 2 = 0 AND MyIn = '1') 
            OR (trans_count mod 2 = 1 AND MyIn = '0') then
        if (trans_count = 3) then
          trans_count := 0 ;
          MyOut <= '1' ;
        else 
          trans_count := trans_count + 1 ;
          MyOut <= '0' ;
        end if ;
      else
        MyOut <= '0' ;
      end if;
    end if ;
  end process ;
end Lab6_arch;