architecture Lab6_arch of Lab6 is
  signal CompRes: STD_LOGIC ;
  signal LastBit: STD_LOGIC ;
  component TwoBitCounter
    port (Clock, Reset, CarryIn: in STD_LOGIC; CarryOut: out STD_LOGIC) ;
  end component ;
  component DFlipFlop
    port (Clock, Clear, D: in STD_LOGIC; Q: out STD_LOGIC) ;
  end component ;
  component XOR2
    port (X, Y: in STD_LOGIC; Z: out STD_LOGIC) ;
  end component ;
begin
  C1: TwoBitCounter port map(CLK, RST, CompRes, MyOut) ;   -- count to 4
  D1: DFlipFlop port map(CLK, RST, MyIn, LastBit) ;        -- save 1 bit
  X1: XOR port map(MyIn, LastBit, CompRes) ;               -- compare  
end Lab6_arch;