CSCI 255, ENGR 274, ECE 212 -- 30 November, 2000

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Examples of VHDL

This is example based on ECE 214 Lab 6. For more information on the history and goals of VHDL return to the 9 November lecture.

Interface specification example

Given in-line below or out-of-line in PDF.


library IEEE;
use IEEE.std_logic_1164.all;

entity Lab6 is
    port (
        RST: in STD_LOGIC;
        MyIn: in STD_LOGIC;
        CLK: in STD_LOGIC;
        MyOut: out STD_LOGIC
    );
end Lab6;
Eight possible values for STD_LOGIC
'U'Unitialized
'X'Forcing Unknown
'0'Forcing 0
'1'Forcing 1
'Z'High Impedance
'W'Weak Unknown
'L'Weak 0
'H'Weak 1
'-'Don't care

Architecture definition -- generic outline

architecture Lab6_arch of Lab6 is
    .... definitions and declarations
begin
    .... concurrent statements
end Lab6_arch ;

Behavioral description

Behavioral description example

Given in-line below or out-of-line in PDF.


architecture Lab6_arch of Lab6 is
  type count_int is range 0 to 3 ;

begin
  process(CLK)
  variable trans_count: count_int ;
  begin
    if CLK'event and CLK = '1' then
      if RST='1' then
        trans_count := 0 ;
        MyOut <= '0' ;
      elsif (trans_count mod 2 = 0 AND MyIn = '1') 
            OR (trans_count mod 2 = 1 AND MyIn = '0') then
        if (trans_count = 3) then
          trans_count := 0 ;
          MyOut <= '1' ;
        else 
          trans_count := trans_count + 1 ;
          MyOut <= '0' ;
        end if ;
      else
        MyOut <= '0' ;
      end if;
    end if ;
  end process ;
end Lab6_arch;

Structural description

Structural description example

Given in-line below or out-of-line in PDF.


architecture Lab6_arch of Lab6 is
  signal CompRes: STD_LOGIC ;
  signal LastBit: STD_LOGIC ;
  component TwoBitCounter
    port (Clock, Reset, CarryIn: in STD_LOGIC; CarryOut: out STD_LOGIC) ;
  end component ;
  component DFlipFlop
    port (Clock, Clear, D: in STD_LOGIC; Q: out STD_LOGIC) ;
  end component ;
  component XOR2
    port (X, Y: in STD_LOGIC; Z: out STD_LOGIC) ;
  end component ;
begin
  C1: TwoBitCounter port map(CLK, RST, CompRes, MyOut) ;   -- count to 4
  D1: DFlipFlop port map(CLK, RST, MyIn, LastBit) ;        -- save 1 bit
  X1: XOR port map(MyIn, LastBit, CompRes) ;               -- compare  
end Lab6_arch;

Dataflow description

Dataflow description example

Given in-line below or out-of-line in PDF.


architecture HalfAdder_Arch of HalfAdder is

begin
  Sum <= '1' when not (In0 = In1) else '0' ;
  Carry <= '1' when In0 = '1' AND In1 = '1' else '0' ;
end HalfAdder_Arch ;

VHDL synthesis

Some VHDL tutorials