CSCI 255, ENGR 274, ECE 212 -- 9 November, 2000

Announcements

Quiz 2
- Thursday, 16 November
- Chapters 3 to 5
Homework 7
Homework 8
Homework 9

Reverse engineering

Timing

circuit

Circuitry

circuit

VHDL

VHDL goals

VHSIC Hardware Description Language
- Very High Speed Integrated Circuits
Developed by IBM, Texas Instruments, and Intermetics in 1983-84
- Under DoD contract
Language and software transfered to IEEE in 1985
Dod requirements
- Hierarchical design
- Library support
- Timing control at all levels
- Sequential control structure
- Strong typing -- like Ada
VHDL 93

Structure of VHDL

Interface specification
- ENTITY specification_name IS
  - begins the interface specification
- PORT( name: mode type .... );
  - mode can be IN, OUT, INOUT, and BUFFER
  - type is BIT or INTEGER RANGE 0 TO 7 or many more
- other physical and logical parameters, if desired
- END specification_name
Architecture specifications
- ARCHITECTURE implementation_name OF specification_name IS
- VHDL implementation with a choice of style
  - procedural -- conventional programming
  - dataflow -- concurrent programming
  - structural -- component connection
- END implementation_name ;
BNF

Structural specification

Provides a means to connect several components
Example from Xilinx Synthesis Technology (XST) User Guide

Structural specification

VHDL Data Types
Process statement
Function example from Xilinx Synthesis Technology (XST) User Guide
Operators
Conditional statements
- if condition then
     statements
  elsif condition then
     statements
  else
     statements
  end if;
- case expression is
  WHEN value =>
  statements
  end case;
Iterative statements
- for var IN 10 DOWNTO 0 LOOP
  statements
  end loop;
- while conditional LOOP
  statements
  end loop;

Behavoural specification

Statements such as
- X <= (A AND B ) OR ( NOT A AND NOT B ) AFTER 12 NS ;

On-line sources