CSCI 255, ENGR 274, ECE 212 -- Halloween, 2000

Announcements

• Quiz 2
  • Tuesday, 14 November
  • Chapters 2 to 5
• Homework 4 solution
• Homework 7
• Homework 8

RAM

• Properties
  • number of words
  • word size
• Connections (minimal)
  • m address input pins
    • to access 2^m words
  • w data input/output pins
    • To access w bits of word
  • chip select input
  • write enable input
• Implementation -- Figure 7.48 (P. 348)
  • Matrix to store bits
  • Row decoders to select row of matrix
  • Sense amplifiers to read/write rows
  • Column decodes to select bytes of retrieved row
  • Data buffers to read/write data off-chip
• Read cycle
  • Load address lines
  • Assert chip select (CS) while write enable (WE) is unasserted
  • Wait the memory access time
  • Read data from chip
  • Unassert chip select
• Write cycle
  • Assert Write Enable while Chip Select is unasserted
  • Load address and data lines
  • Assert Chip Select
  • Wait
  • Unassert
• Rows and Columns
  • Divide the address space into two address fields -- row and column
  • Add Row Address Strobe (RAS) and Column Address Strobe (CAS) controls
  • Read/Write cycles now use RAS and CAS -- Figure 7.54 (p. 362)

Sample Read and Write cycle for SDRAM taken from Intel's PC SDRAM Specification.

Static vs. Dynamic RAM

• Static RAM
  • Generally implemented with six transistors -- Figure 7.46 (p. 357)
  • Holds data as long as power is present
  • Usually faster and more expensive
  • IBM's Understanding Static RAM Operation
• Dynamic RAM
  • Implemented with one transistor -- Figure 7.51 (p. 360)
  • Need periodic refresh
  • Usually slower and cheaper
  • IBM's Understanding DRAM Operation

Varieties

Fast Page Mode

Allows faster access of data within pages

EDO -- Extended Data Out

Data stays valid after CAS is unasserted

SDRAM -- Synchronous DRAM

Internal operations of memory module is synchronous with system clock

PC133

Intel specification for 133 Mhz SDRAM

DDR DRAM -- Double Data Rate DRAM

Bytes can be read of both edges of clock -- See JEDEC's specification

SPD -- Serial Presence Detect

A small EEPROM contained on a DIMM which contains detailed information about DIMM characteristics -- See IBM's application note

RDRAM -- RAMBUS DRAM

New memory specification supporting a high transfer rate over narrower buses -- See IBM's Direct Rambus Memory System Overview

Memory controller

Memory controllers generate the signals needed to read and write data from a RAM. They are responsible for the correct sequencing of control signals. Let's take a look at the figures of Section 7.6.5 (pp. 367-372).

Halloween images obtained from Ben and Jerry's.