CSCI 255, ENGR 274, ECE 212 -- Halloween, 2000


Trick or Treat


SD RAM Read and Write Commands
Sample Read and Write cycle for SDRAM taken from Intel's PC SDRAM Specification.


Static vs. Dynamic RAM

Logic design drives me batty


Fast Page Mode
Allows faster access of data within pages
EDO -- Extended Data Out
Data stays valid after CAS is unasserted
SDRAM -- Synchronous DRAM
Internal operations of memory module is synchronous with system clock
Intel specification for 133 Mhz SDRAM
DDR DRAM -- Double Data Rate DRAM
Bytes can be read of both edges of clock -- See JEDEC's specification
SPD -- Serial Presence Detect
A small EEPROM contained on a DIMM which contains detailed information about DIMM characteristics -- See IBM's application note
New memory specification supporting a high transfer rate over narrower buses -- See IBM's Direct Rambus Memory System Overview

Who's watching

Memory controller

Memory controllers generate the signals needed to read and write data from a RAM. They are responsible for the correct sequencing of control signals. Let's take a look at the figures of Section 7.6.5 (pp. 367-372).

Halloween images obtained from Ben and Jerry's.