CSCI 255, ENGR 274, ECE 212 -- 26 October, 2000

Old stuff

• Partial Homework 4 soluation
• Hazards and glitches
  • Static-0 Hazards do not occur in two-level AND-OR circuits or NAND-NAND circuits
  • Similarly, Static-1 hazards do not occur in two-level OR-AND circuits or NOR-NOR circuits
• Data and ready vs. dual rail encoding?

Registers

• Connections
  • m inputs
  • m outputs
  • clock
  • write/input enable
• Variations
  • complementary outputs
  • output enable with tri-states
  • register files
    • multi-ported register files

Shift registers

• Connections
  • shift-in input
  • shift-out input
  • clock
  • m outputs -- parallel out
  • m inputs -- parallel load
• Connecting shift registers
• A universal shift registers
• Asynchronous shift registers with dual rail encoding

Let me count the ways

• Connections
  • clock
  • clear
  • load
  • m inputs
  • m outputs
  • count enable
  • count overflow
• Variations
  • Binary counters
  • Decode (BCD) counters
  • Gray code counters
  • Ring counters
• Cascaded counters
• Different starts and stops

Making an prime counter

• The next state table
• Using the excition tables
• Implementation