CSCI 255, ENGR 274, ECE 212 -- 24 October, 2000

Flip-flops

• J-K flip flop
• R-S flip flop
• D flip flop
• T flip flop

Three-phases with flip-flops

• D flip-flop
• J-K flip-flop
• T flip-flop

Clocks

• Problems of cascading flip-flops
  • illustrated with the D flip-flop
• Cost of edge-triggered flip-flops
  • Figure 6.25 (p. 297) vs. Figure 6.32 (p. 302)
• Narrow-width clocks
  • Clock event (high clock time) must be less than fastest propagation
  • Clock period (high+low clock time) must be greater than slowest propagation
• Multiphase clocking (Fig 6.35 & 6.36, p. 304)
  • Use in CMOS circuits
  • a personal aside

No Clocks

• The Synchronous and Asynchronous world
  • In the world of communcations
    • UART -- Universal Asynchronous Receiver/Transmitter
• Metastability and synchronizer failure
• Self-timed systems
  • Use of request and acknowledgment lines -- Fig 6.55
  • Dual-rail signalling
  • Muller C-element
• For more recent information
  • Scanning the Technology: Applications of Asynchronous Circuits
  • Kicking out the Clock
• Debouncing switches -- Figure 6.56 (p. 317)