| Type | Inputs are sampled | Outputs are valid |
|---|---|---|
| Unclocked latch | Always | Progation delay from input change |
| Level-sensitive latch | Clock high | Progation delay from input change |
| Postive-edge flip-flop | Clock low-to-high transition | Progation delay from rising edge of clock |
| Negative-edge flip-flop | Clock high-to-low transition | Progation delay from falling edge of clock |